View FSBM10SH60_4904628.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2002 fairchild semiconductor corporation may 2002 FSBM10SH60 rev. a, may 2002 FSBM10SH60 spm tm (smart power module) general description FSBM10SH60 is an advanced smart power module (spm) that fairchild has newly developed and designed to provide very compact and low cost, yet high performance ac motor drives mainly targeting high speed low-power inverter- driven application like washing machines. it combines optimized circuit protection and drive matched to low-loss igbts. highly effective short-circuit current detection/ protection is realized through the use of advanced current sensing igbt chips that allow continuous monitoring of the igbts current. system reliability is further enhanced by the integrated under-voltage lock-out protection. the high speed built-in hvic provides opto-coupler-less igbt gate driving capability that further reduce the overall size of the inverter system design. in addition the incorporated hvic facilitates the use of single-supply drive topology enabling the FSBM10SH60 to be driven by only one drive supply voltage without negative bias. inverter current sensing application can be achieved due to the divided negative dc terminals. features ? ul certified no. e209204 ? 600v-10a 3-phase igbt inverter bridge including control ics for gate driving and protection ? divided negative dc-link terminals for inverter current sensing applications ? single-grounded power supply due to built-in hvic ? typical switching frequency of 15khz ? inverter power rating of 0.4kw / 100~253 vac ? isolation rating of 2500vrms/min. ? very low leakage current due to using ceramic substrate ? adjustable current protection level by varying series resistor value with sense-igbts applications ? ac 100v ~ 253v three-phase inverter drive for small power (0.4kw) ac motor drives ? home appliances applications requiring high switching frequency operation like washing machines drive system ? application ratings: - power : 0.4 kw / 100~253 vac - switching frequency : typical 15khz (pwm control) - 100% load current : 3.0a (irms) - 150% load current : 4.5a (irms) for 1 minute external view fig. 1. top view bottom view mm 60 mm 31 mm 60 mm 3 mm 60 mm 60 mm 31 mm 31 mm 60 mm 60 mm 3
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 integrated power functions ? 600v-10a igbt inverter for three-phase dc/ac power conversion (please refer to fig. 3) integrated drive, protection and system control functions ? for inverter high-side igbts: gate drive circuit, high voltage isolated high-speed level shifting control circuit under-voltage (uv) protection note) available bootstrap circuit example is given in figs. 10, 15and 16. ? for inverter low-side igbts: gate drive circuit, short circuit protection (sc) control supply circuit under-voltage (uv) protection ? fault signaling: corresponding to a sc fault (low-side igbts) or a uv fault (low-side supply) ? input interface: 5v cmos/lsttl compatible, schmitt trigger input pin configuration fig. 2. top view v cc(l) com (l) in (ul) in (vl) in (wl) com (l) v fo c fod c sc r sc in (uh) v cc(uh) v b(u) v s(u) in (vh) com (h) v cc(vh) v b(v) v s(v) in (wh) v cc(wh) v b(w) v s(w) nc nc n u n v n w u v w p v cc(l) com (l) in (ul) in (vl) in (wl) com (l) v fo c fod c sc r sc in (uh) v cc(uh) v b(u) v s(u) in (vh) com (h) v cc(vh) v b(v) v s(v) in (wh) v cc(wh) v b(w) v s(w) nc nc n u n v n w u v w p
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 pin descriptions pin number pin name pin description 1v cc(l) low-side common bias voltage for ic and igbts driving 2com (l) low-side common supply ground 3in (ul) signal input terminal for low-side u phase 4in (vl) signal input terminal for low-side v phase 5in (wl) signal input terminal for low-side w phase 6com (l) low-side common supply ground 7v fo fault output terminal 8c fod capacitor for fault output duration time selection 9c sc capacitor (low-pass filter) for short-current detection input 10 r sc resistor for short-circuit current detection 11 in (uh) signal input terminal for high-side u phase 12 v cc(uh) high-side bias voltage for u phase ic 13 v b(u) high-side bias voltage for u phase igbt driving 14 v s(u) high-side bias voltage ground for u phase igbt driving 15 in (vh) signal input terminal for high-side v phase 16 com (h) high-side common supply ground 17 v cc(vh) high-side bias voltage for v phase ic 18 v b(v) high-side bias voltage for v phase igbt driving 19 v s(v) high-side bias voltage ground for v phase igbt driving 20 in (wh) signal input terminal for high-side w phase 21 v cc(wh) high-side bias voltage for w phase ic 22 v b(w) high-side bias voltage for w phase igbt driving 23 v s(w) high-side bias voltage ground for w phase igbt driving 24 nc no connection 25 nc no connection 26 n u negative dc?link input terminal for u phase 27 n v negative dc?link input terminal for v phase 28 n w negative dc?link input terminal for w phase 29 u output terminal for u phase 30 v output terminal for v phase 31 w output terminal for w phase 32 p positive dc?link input terminal
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 internal equivalent circuit and input/output pins note: 1. inverter low-side is composed of three sense-igbts including freewheeling diodes for each igbt and one control ic which has g ate driving, current sensing and protection functions. 2. inverter power side is composed of four inverter dc-link input terminals and three inverter output terminals. 3. inverter high-side is composed of three normal-igbts including freewheeling diodes and three drive ics for each igbt. fig. 3. bottom view com(l) vcc in(ul) in(vl) in(w l) vfo c(fod) c(sc) out(ul) out(vl) out(wl) n u (26) n v (27) n w (28) u (29) v (30) w (31) p (32) (23) v s(w) (22) v b(w) (19) v s(v) (18) v b(v) (9) c sc (8) c fod (7) v fo (5) in (w l) (4) in (v l) (3) in (ul) (2) com (l) (1) v cc(l) (10) r sc nc (25) nc (24) (6) com (l) vcc vb out com vs in vb vs out in com vcc vcc vb out com vs in (21) v cc(wh) (20) in (w h) (17) v cc(wh) (15) in (w h) (16) com (h) (14) v s(u) (13) v b(u) (12) v cc(uh) (11) in (uh)
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 absolute maximum ratings inverter part (t c = 25c, unless otherwise specified) note 1. it would be recommended that the average junction temperature should be limited to t j 125 c (@t c 100 c) in order to guarantee safe operation. control part (t c = 25c, unless otherwise specified) total system fig. 4. t c measurement point item symbol condition rating unit supply voltage v dc applied to dc - link 450 v supply voltage (surge) v pn(surge) applied between p- n 500 v collector-emitter voltage v ces 600 v each igbt collector current i c t c = 25c 10 a each igbt collector current i c t c = 100c 8 a each igbt collector current (peak) i cp t c = 25c 20 a collector dissipation p c t c = 25c per one chip 42 w operating junction temperature t j (note 1) -55 ~ 150 c item symbol condition rating unit control supply voltage v cc applied between v cc(h) - com (h) , v cc(l) - com (l) 18 v high-side control bias voltage v bs applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 20 v input signal voltage v in applied between in (uh) , in (vh) , in (wh) - com (h) in (ul) , in (vl) , in (wl) - com (l) -0.3 ~ 6.0 v fault output supply voltage v fo applied between v fo - com (l) -0.3~v cc +0.5 v fault output current i fo sink current at v fo pin 5 ma current sensing input voltage v sc applied between c sc - com (l) -0.3~v cc +0.5 v item symbol condition rating unit self protection supply voltage limit (short circuit protection capability) v pn(prot) applied to dc - link, v cc = v bs = 13.5 ~ 16.5v t j = 125c, non-repetitive, less than 6 s 400 v module case operation temperature t c note fig.4 -20 ~ 100 c storage temperature t stg -50 ~ 150 c isolation voltage v iso 60hz, sinusoidal, ac 1 minute, connection pins to heat-sink plate 2500 v rms case temperature(t case temperature(t case temperature(t case temperature(t c c c c ) ) ) ) detecting point detecting point detecting point detecting point ceramic ceramic ceramic ceramic substrate substrate substrate substrate case temperature(t case temperature(t case temperature(t case temperature(t c c c c ) ) ) ) detecting point detecting point detecting point detecting point ceramic ceramic ceramic ceramic substrate substrate substrate substrate
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 absolute maximum ratings thermal resistance note: 2. for the measurement point of case temperature(t c ), please refr to fig. 4. electrical characteristics inverter part (t j = 25c, unless otherwise specified) note: 3. t on and t off include the propagation delay time of the internal drive ic. t c(on) and t c(off) are the switching time of igbt itself under the given gate driving condition internally. for the detailed information, please see fig. 5. item symbol condition min. typ. max. unit junction to case thermal resistance r th(j-c)q each igbt under inverter operating condition - - 2.93 c/w r th(j-c)f each fwdi under inverter operating condition - - 3.71 c/w contact thermal resistance r th(c-f) ceramic substrate (per 1 module) thermal grease applied - - 0.06 c/w item symbol condition min. typ. max. unit collector - emitter saturation voltage v ce(sat) v cc = v bs = 15v v in = 0v i c = 10a, t j = 25c - - 2.8 v i c = 10a, t j = 125c - - 2.9 v fwdi forward voltage v fm v in = 5v i c = 10a, t j = 25c - - 2.3 v i c = 10a, t j = 125c - - 2.1 v switching times t on v pn = 300v, v cc = v bs = 15v i c = 10a, t j = 25c v in = 5v ? 0v, inductive load (high-low side) (note 3) -0.37- us t c(on) -0.12- us t off -0.53- us t c(off) -0.2-us t rr -0.1-us collector - emitter leakage current i ces v ce = v ces , t j = 25c - - 250 ua
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 fig. 5. switching time definition fig. 6. experimental results of switching waveforms test condition: vdc=300v, vcc=15v, l=500uh (inductive load), t c =25 c t rr i c v ce v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce 100% i c (a) turn-on t rr i c v ce v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce 100% i c (a) turn-on (b) turn-off i c v ce v in t off t c(off) 10% v ce 10% i c v in(off) (b) turn-off i c v ce v in t off t c(off) 10% v ce 10% i c v in(off) (a) turn-on v ce : 100v/div. i c : 5a/div. time : 100ns/div. (b) turn-off v ce : 100v/div. i c : 5a/div. time : 100ns/div. (a) turn-on v ce : 100v/div. i c : 5a/div. time : 100ns/div. (b) turn-off v ce : 100v/div. i c : 5a/div. time : 100ns/div.
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 electrical characteristics control part (t j = 25c, unless otherwise specified) note: 4. short-circuit current protection is functioning only at the low-sides. it would be recommended that the value of the external sensing resistor (r sc ) should be selected around 56 ? in order to make the sc trip-level of about 15a at the shunt resistors (r su ,r sv ,r sw ) of 0 ? . for the detailed information about the relationship between the external sensing resistor (r sc ) and the shunt resistors (r su ,r sv ,r sw ), please see fig. 7. 5. the fault-out pulse width t fod depends on the capacitance value of c fod according to the following approximate equation : c fod = 18.3 x 10 -6 x t fod [f] item symbol condition min. typ. max. unit control supply voltage v cc applied between v cc(h) ,v cc(l) - com 13.5 15 16.5 v high-side bias voltage v bs applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 13.5 15 16.5 v quiescent v cc supply cur- rent i qccl v cc = 15v in (ul, vl, wl) = 5v v cc(l) - com (l) --26ma i qcch v cc = 15v in (uh, vh, wh) = 5v v cc(u) , v cc(v) , v cc(w) - com (h) - - 130 ua quiescent v bs supply cur- rent i qbs v bs = 15v in (uh, vh, wh) = 5v v b(u) - v s(u) , v b(v) -v s(v) , v b(w) - v s(w) - - 420 ua fault output voltage v foh v sc = 0v, v fo circuit: 4.7k ? to 5v pull-up 4.5 - - v v fol v sc = 1v, v fo circuit: 4.7k ? to 5v pull-up - - 1.1 v pwm input frequency f pwm t c 100c, t j 125c - 15 - khz allowable input signal blanking time considering leg arm-short t dead -20c t c 100c 1 - - us short circuit trip level v sc(ref) t j = 25c, v cc = 15v (note 4) 0.45 0.51 0.56 v sensing voltage of igbt current v sen -20c t c 100c, @ r sc = 82 ? , r su = r sv = r sw = 0 ? and i c = 10a (note fig. 16) 0.37 0.45 0.56 v supply circuit under- voltage protection uv ccd t j 125c detection level 11.5 12 12.5 v uv ccr reset level 12 12.5 13 v uv bsd detection level 7.3 9.0 10.8 v uv bsr reset level 8.6 10.3 12 v fault-out pulse width t fod c fod = 33nf (note 5) 1.4 1.8 2.0 ms on threshold voltage v in(on) high-side applied between in (uh) , in (vh) , in (wh) - com (h) --0.8v off threshold voltage v in(off) 3.0 - - v on threshold voltage v in(on) low-side applied between in (ul) , in (vl) , in (wl) - com (l) --0.8v off threshold voltage v in(off) 3.0 - - v
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 fig. 7. r sc variation by change of shunt resistors (r su , r sv , r sw ) for short-circuit protection @ around 100% rated current trip (i c = 10a) @ around 150% rated current trip (i c = 15a) 1 2 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0 10 20 30 40 50 60 70 80 90 100 r sc [ ? ] r su ,r sv ,r sw [ ? ] 1 2 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0 10 20 30 40 50 60 70 80 90 100 r sc [ ? ] r su ,r sv ,r sw [ ? ]
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 mechanical characteristics and ratings fig. 8. flatness measurement position of the ceramic substrate note: 6. do not make over torque or mounting screws. much mounting torque may cause ceramic cracks and bolts and al heat-fin destructi on. 7. avoid one side tightening stress. fig.9 shows the recommended torque order for mounting screws. uneven mounting can cause the spm ceramic substrate to be damaged. fig. 9. mounting screws torque order (1 2) item condition limits units min. typ. max. mounting torque mounting screw: m4 (note 6 and 7) recommended 10kg?cm 8 10 12 kg?cm recommended 0.98n?m 0.78 0.98 1.17 n?m ceramic flatness note fig.8 0 - +120 um weight -35- g (+) (+) (+) datum line (+) (+) (+) datum line 1 2 1 2
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 recommended operating conditions ics internal structure and input/output conditions note: 1. one lvic drives three sense-igbts and can do short-circuit current protection also. three sense emitters are commonly connect ed to r sc terminal to detect short-circuit current. low-side part of the inverter consists of three sense-igbts 2. one hvic drives one normal-igbt. high-side part of the inverter consists of three normal-igbts 3. each ic has under voltage detection and protection function. 4. the logic input is compatible with standard cmos or lsttl outputs. 5. r p c p coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each spm gating input pin. 6. it would be recommended that the bootstrap diode, d bs , has soft and fast recovery characteristics. fig. 10. item symbol condition value unit min. typ. max. supply voltage v pn applied between p - n - 300 400 v control supply voltage v cc applied between v cc(h) - com, v cc(l) - com 13.5 15 16.5 v high-side bias voltage v bs applied between v b(u) - v s(u) , v b(v) - v s(v) , v b(w) - v s(w) 13.5 15 16.5 v blanking time for preventing arm-short t dead for each input signal 1 - - us pwm input signal f pwm t c 100c, t j 125c - 15 - khz input on threshold voltage v in(on) applied between u in ,v in , w in - com 0 ~ 0.65 v input off threshold voltage v in(off) applied between u in ,v in , w in - com 4 ~ 5.5 v level shift hvic hvic hvic hvic uv detect pulse filter r r s q in in in in (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) com com com com vs vs vs vs (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) vcc vcc vcc vcc (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) 15v line 15v line 15v line 15v line uv protection sc protection time delay sc latch_up in in in in (ul,vl,wl) (ul,vl,wl) (ul,vl,wl) (ul,vl,wl) pulse generator (hysterisis) buffer output (ul,vl,wl) soft_off control vcc vcc vcc vcc (l) (l) (l) (l) uv detect time delay bandgap reference fault output duration v v v v fo fo fo fo uv latch_up c c c c fod fod fod fod sc detection lvic lvic lvic lvic p p p p vb vb vb vb (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) (uh,vh,wh) 5v line 5v line 5v line 5v line 5v line 5v line 5v line 5v line r p c pl c fod r p c ph n n n n u u u u , n , n , n , n v v v v , n , n , n , n w w w w c bsc d bs r bs r f pulse generator r p c pf c bp15 c bs u, v, w u, v, w u, v, w u, v, w c sc r su , r sv , r sw c sc input signal fault signal input signal r sc
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 time charts of spms protective function p1 : normal operation - igbt on and conducting current p2 : under voltage detection p3 : igbt gate interrupt p4 : fault signal generation p5 : under voltage reset p6 : normal operation - igbt on and conducting current fig. 11. under-voltage protection (low-side) p1 : normal operation - igbt on and conducting current p2 : under voltage detection p3 : igbt gate interrupt p4 : no fault signal p5 : under voltage reset p6 : normal operation - igbt on and conducting current fig. 12. under-voltage protection (high-side) internal igbt gate-emitter voltage input signal output current fault output signal control supply voltage p1 p2 p3 p4 p6 p5 uv detect uv reset internal igbt gate-emitter voltage input signal output current fault output signal control supply voltage v bs p1 p2 p3 p4 p6 p5 uv detect uv reset
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 p1 : normal operation - igbt on and conducting currents p2 : short-circuit current detection p3 : igbt gate interrupt / fault signal generation p4 : igbt is slowly turned off p5 : igbt off signal p6 : igbt on signal - but igbt cannot be turned on during the fault-output activation p7 : igbt off state p8 : fault-output reset and normal operation start fig. 13. short-circuit current protection (low-side operation only) internal igbt gate-emitter voltage input signal output current sensing voltage fault output signal p1 p2 p3 p4 p6 p5 p7 p8 sc reference voltage (0.5v) rc filter delay sc detection
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 note it would be recommended that by-pass capacitors for the gating input signals, in (xx) should be placed on the spm pins and on the both sides of cpu and spm for the fault output signal, v fo , as close as possible. fig. 14. recommended cpu i/o interface circuit fig. 15. recommended bootstrap operation circuit and parameters cpu com 5v-line 1.2nf 0.47nf 1nf ? 4.7k ? 4.7k ? 4.7k ,, in (ul) in (vl) in (wl) ,, in (uh) in (vh) in (wh) v fo ? 100 ? 100 ? 100 1nf FSBM10SH60 15v-line 20 ? 220uf 0.1uf 1000uf 0.1uf one-leg diagram of FSBM10SH60 vcc in com vb ho vs vcc in com out inverter output p n these values depend on pwm control algorithm
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 note: 1. r p c pl /r p c ph coupling at each spm input is recommended in order to prevent input signals? oscillation and it should be as close as possible to each spm input pin. 2. by virtue of integrating an application specific type hvic inside the spm, direct coupling to cpu terminals without any opto- coupler or transformer isolation is possible. 3. v fo output is open collector type. this signal line should be pulled up to the positive side of the 5v power supply with approxim ately 4.7k ? resistance. please refer to fig. 16. 4. c sp15 of around 7 times larger than bootstrap capacitor c bs is recommended. 5. v fo output pulse width should be determined by connecting an external capacitor(c fod ) between c fod (pin8) and com (l) (pin2). (example : if c fod = 5.6 nf, then t fo = 300 s (typ.)) please refer to the note 5 for calculation method. 6. each input signal line should be pulled up to the 5v power supply with approximately 4.7k ? resistance (other rc coupling circuits at each input may be needed depending on the pwm control scheme used and on the wiring impedance of the system?s printed circuit board). approximately a 0 .22~2nf by-pass capacitor should be used across each power supply connection terminals. 7. to prevent errors of the protection function, the wiring around r sc , r f and c sc should be as short as possible. 8. in the short-circuit protection circuit, please select the r f c sc time constant in the range 3~4 s. r f should be at least 30 times larger than r sc . (recommended example: r sc = 56 ? , r f = 3.9k ? , c sc = 1nf and r su = r sv = r sw = 0 ? ) 9. for the use of shunt resistors ( r su , r sv , r sw ), please see fig. 7 in order to select the proper r sc . 10.each capacitor should be mounted as close to the pins of the spm as possible. 11.to prevent surge destruction, the wiring between the smoothing capacitor and the p&n pins should be as short as possible. t he use of a high frequency non- inductive capacitor of around 0.1~0.22 uf between the p&n pins is recommended. 12.relays are used at almost every systems of electrical equipments of home appliances. in these cases, there should be suffic ient distance between the cpu and the relays. it is recommended that the distance be 5cm at least fig. 16. application circuit com(l) vcc in(ul) in(vl) in(w l) vfo c(fod) c(sc) out(ul) out(vl) out(wl) n u (26) n v (27) n w (28) u (29) v (30) w (31) p (32) (23) v s(w ) (22) v b(w ) (19) v s(v) (18) v b(v) (9) c sc (8) c fod (7) v fo (5) in (w l) (4) in (vl) (3) in (ul) (2) com (l) (1) v cc(l) (10) r sc nc (24) nc (25) (6) com (l) vcc vb out com vs in vb vs out in com vcc vcc vb out com vs in (21) v cc(wh) (20) in (w h) (17) v cc(vh) (15) in (vh) (16) com (h) (14) v s(u) (13) v b(u) (12) v cc(uh) (11) in (uh) fault 15v line c bs c bsc r bs d bs c bs c bsc r bs d bs c bs c bsc r bs d bs c sp15 c spc15 c fod 5v line r p c pl c bpf r p r p r p c pl c pl 5v line c ph r p c ph r p c ph r p r s r s r s r s r s r s r s m vdc c dcs gating uh gating vh gating w h gating w l gating vl gating ul c pf c c c c p p p p u u u u r fu r fv r fw r su r sv r sw c fu c fv c fw u-phase current v-phase current w-phase current r f c sc r sc
?2002 fairchild semiconductor corporation FSBM10SH60 rev. a, may 2002 detailed package outline drawings
?2002 fairchild semiconductor corporation rev. h5 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. star*power is used under license acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos? ensigna? fact? fact quiet series? fast ? fastr? frfet? globaloptoisolator? gto? hisec? i 2 c? isoplanar? littlefet? microfet? micropak? microwire? optologic? optoplanar? pacman? pop? power247? powertrench ? qfet? qs? qt optoelectronics? quiet series? slient switcher ? smart start? spm? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet ? vcx?

▲Up To Search▲

Price & Availability of FSBM10SH60

	To Download FSBM10SH60 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .